The present invention relates to a semiconductor integrated circuit which incorporates voltage regulators for stepping down the externally-supplied power voltage, and to a technique which is applied effectively to data processing systems, such as portable information terminals, having their semiconductor chips required to be smaller in size and power consumption.
Among semiconductor integrated circuits having internal circuits which operate based on an internal power voltage (Vint: 1.8 V, 1.5 V, etc.) lower than an external power voltage (Vext: 3.3 V, 5.0 V, etc.), there are some integrated circuits having a voltage step-down circuit which steps down an external power voltage to produce an internal power voltage. With the intention of reducing the voltage drop of the internal power voltage caused by the parasitic resistance of wires from the voltage step-down circuit to the internal circuits, there is known a technique of building multiple voltage step-down circuits on the chip and laid near the power pads so that the voltage drop of the external power voltage caused by the parasitic resistance of the wires from the power pads to the voltage step-down circuits is reduced.
Publications pertinent to this technique include Japanese Patent Unexamined Publications No. Hei 9 (1997)-289288 and No. Hei 2 (1990)-224267.
The inventors of the present invention have studied these prior arts to find the following affairs.
The prior arts are designed to lay voltage step-down circuits near the power pads so as to minimize the voltage drop of the internal power voltage caused by the parasitic resistance of the wires from the voltage step-down circuits to the internal circuits and minimize the voltage drop of the external power voltage on the wires from the power pads to the voltage step-down circuits. However, these prior arts do not consider the increase of chip area due to the on-chip provision of the voltage step-down circuits and do not present clearly the scheme of reducing this overhead chip area.
The inventors of the present invention have contemplated to foster the reduction of power consumption by use of a step-down power voltage, and found that it is beneficial to control the step-down voltage level depending on the operational state of the semiconductor integrated circuit and use the step-down power voltage or external power voltage selectively in controlling the threshold voltage of MOS transistors by varying the substrate voltage for the reduction of sub-threshold leak current of the circuits which operate based on the step-down power voltage.
An object of the present invention is to provide a semiconductor integrated circuit which is capable of minimizing the increase of chip area caused by the on-chip provision of voltage regulators which step down the external power voltage and also stabilizing the step-down voltage.
Another object of the present invention is to provide a semiconductor integrated circuit which is capable of advancing the power conservation based on the use of step-down voltages.
Still another object of the present invention is to provide a technique which facilitates the design of semiconductor integrated circuits which are intended to minimize the increase of chip area caused by the on-chip provision of voltage regulators for stepping down the external power voltage and stabilize the step-down voltage.
The above, other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Among the affairs of the present invention disclosed in this specification, representatives are briefed as follows.
(1) Buffer and Protection Circuit Area
The inventive semiconductor integrated circuit has on a semiconductor chip (10) a first area (1) for laying external terminals (20) such as the electrode pads for the input/output signals and power voltages. The first area (1) is adjoined by a second area (2) for laying buffers and protection circuits pertinent to the input/output signals and power voltages. The second area (2) is also used for laying multiple voltage regulators (150-157) which step down a first power voltage (Vext) supplied from the outside of the semiconductor chip (10) to produce at least one kind of internal power voltage (Vint) which is lower than Vext. The voltage regulators are laid in the area having its width generally determined from the layout width of buffers and protection circuits and at positions near the external terminals of the first power voltage and ground voltage. There is a third area for laying first internal circuits which operate based on the internal power voltage.
The portions of the second area near the external terminals of the first power voltage and ground voltage are not used to lay buffers, which are laid solely near the external terminals of signals, and accordingly these portions are inherently less crowded and readily available for the layout of voltage regulators. The buffers and protection circuits are basically provided for individual external terminals and they are smaller in number as compared with circuits in the whole semiconductor integrated circuit, and the area corresponding to the second area is conceived to be an area having a space where the voltage regulators can be formed.
By using the second area having its width generally determined from the layout width of buffers and protection circuits to lay multiple voltage regulators, it is relatively easy to increase the number of regulators without increasing the chip area proportionally. Accordingly, this layout scheme readily minimizes the increase of chip area due to the on-chip provision of voltage regulators which step down the external power voltage, and moreover achieves the stabilization of the step down voltage by allowing the supply of a large current to the first internal circuits.
(2) Main Power Line
The semiconductor integrated circuit has power lines including a main power line (L20) which is connected to the outputs of the voltage regulators for distributing the internal power voltage to the first internal circuits. Preferably, the main power line is formed to be a closed loop, so that the internal power voltage is constant throughout the power line and supplied stably to many scattering circuits located on the semiconductor chip.
The main power line is laid to have a generally equal parasitic resistance between output nodes of voltage regulators, so that the internal power voltage has an even voltage level throughout the line. This is attainable by making a generally equal distance between output nodes of voltage regulators on the main power line.
For coping with a limited area available for the voltage regulators to be integrated on the semiconductor chip, it is advantageous to adopt series voltage regulators, with a stabilizing capacitor (C10) being attached externally to the chip by the provision of an external terminal (20A-2) which is connected to the main power line.
(3) Signal Level Converting Circuit
In regard to the transfer of signals between a circuit which operates based on the first power voltage and a circuit which operates based on the internal power voltage, the former circuit can send the signal directly to the latter circuit. In another case of putting a signal from the latter circuit to the former circuit, the former circuit receives a signal level lower than the power voltage, for example, the input signal level of a CMOS circuit can be logically intermediate, causing possibly the creation of a undesired through-current. For preventing this event from occurring, second internal circuits which operate based on the first power voltage are provided with level converting circuits (G3) which convert the output signals of the first internal circuits to have logic levels derived from the first power voltage. Specifically, for example, a first logic circuit provides the output signal for a buffer in the second area via the level converting circuit.
(4) Reference Voltage Generation Circuit
In case the voltage regulators necessitate a reference voltage for producing a specified step-down voltage, a reference voltage generation circuit (60) is formed as a second internal circuit which operates based on the first power voltage. The reference voltage is supplied to the voltage regulators through an open-loop reference voltage line (L10) if it is intended to minimize the antenna effect of the line. The reference voltage supply line is laid to run generally along the layout of voltage regulators, with a grounded shield line being formed on the same wiring layer. Additional shield lines or shield areas may be formed above and below the reference voltage supply line, so that the fluctuation of reference voltage caused by crosstalk is minimized.
With the intention of coping with the disparity of characteristics of semiconductor integrated circuits, the reference voltage may be produced by a reference voltage generator (100) having its characteristics determined by trimming information which is held in an electrically-erasable nonvolatile memory. The trimming information is calculated based on the measurement of characteristics of individual reference voltage generators during the wafer probe test and stored in the nonvolatile memory (135). At the initializing process of the semiconductor integrated circuit, the reference voltage generator reads out to latch the trimming information out of the nonvolatile memory and produces a reference voltage in accordance with the latched trimming information so as to offset the deviated characteristics.
The reference voltage generation circuit may be designed to produce a reference voltage which is selected out of multiple kinds of reference voltages. For example, in case the semiconductor integrated circuit operates in synchronism with a clock signal, the reference voltage generation circuit produces a lower reference voltage in order to provide a lower clock frequency for the low speed operation of the first circuits, or produces a higher reference voltage in order to provide a higher clock frequency for the high speed operation.
The selection of reference voltage may be controlled in response to a command which is given by a control means, such as the CPU (120), depending on the operation mode to the reference voltage generation circuit. Specifically, for example, a semiconductor integrated circuit of a microprocessor or data processor is designed to select the lower reference voltage in the standby mode or sleep mode, and select the higher reference voltage in the active mode.
(5) Regulator Activation Control
With the intention of reducing the power consumption of the semiconductor integrated circuit, it is designed to include as a second internal circuit a regulator activation control means (70) for turning on or off the voltage regulators. The activation control means can control each of or each group of voltage regulators separately. Specifically, for example, all voltage regulators are turned on in the active mode, and only part of regulators are turned on in the standby mode or sleep mode. Alternatively, part of the regulators are designed to have a smaller power capacity, and only these regulators are turned on in the standby mode or sleep mode.
One or a small number of sub voltage regulators (80) may be formed in a fourth area as second internal circuits which are based on the first power voltage, with the regulator activation control means (70) being adapted to turn on the voltage regulator of the second area in response to a first operation mode such as the active mode of the semiconductor integrated circuit and turn on the sub voltage regulator in response to a second operation mode such as the standby mode or sleep mode of the semiconductor integrated circuit.
(6) Switching Power Regulator Control
The on-chip voltage regulators of the semiconductor integrated circuit may not suffice for the power supply. For coping with this matter readily, the semiconductor chip having several voltage regulators is designed to include as a second circuit a driver control circuit (90) for a switching power regulator which is assumed to be attached externally, with some external terminals (20B-1,20B-2) being allotted to the output signals of the external driver control circuit.
The external switching regulator, when attached to the semiconductor integrated circuit, has its voltage output terminal connected to a certain external terminal (20B-3), which is connected with the output nodes of voltage regulators on the main power line which supplies the internal power voltage to the first internal circuits. In this case, the on-chip voltage regulators do not need to operate. The semiconductor integrated circuit includes a deactivation control means (70,135) which deactivates one of the voltage regulators or the driver control circuit of switching regulator permanently. Specifically, for example, the deactivation control means is a power fuse or a flash memory fuse formed of an electrically-erasable nonvolatile memory element.
The semiconductor integrated circuit needs to include only the driver control circuit which merely takes up a relatively small chip area, while allowing for the selection of output power transistor of external switching regulator depending on the power capacity required.
(7) Substrate Bias Control Circuit
Switching elements such as MOS (metal oxide semiconductor) transistors or MIS (metal insulated semiconductor) transistors have their operation speed and sub-threshold leak current depending on their threshold voltage. The operation frequency can be raised by lowering the threshold voltage, however, setting a too low threshold voltage will fail to cutting off completely MOS transistors due to their sub-threshold characteristics, resulting in an increased sub-threshold leak current and an extremely large power dissipation of the semiconductor integrated circuit. Applying a forward substrate bias voltage to a switching transistor lowers the threshold voltage, resulting in a much faster operation, whereas applying a reverse substrate bias voltage to a switching transistor raises the threshold voltage, resulting in a smaller sub-threshold leak current in the nonconductive state and a smaller power dissipation.
The substrate biasing is to make the substrate voltage different from the source voltage of switching transistors. If an n-channel MOS transistor is brought to have a substrate voltage lower than the source voltage (i.e., state of reverse bias), the threshold voltage becomes higher as compared with the state of no bias, or if it is brought to have a substrate voltage higher than the source voltage (i.e., state of forward bias), the threshold voltage becomes lower as compared with the state of no bias. If a p-channel MOS transistor is brought to have a substrate voltage higher than the source voltage (i.e., state of reverse bias), the threshold voltage becomes higher as compared with the state of no bias, or if it is brought to have a substrate voltage lower than the source voltage (i.e., state of forward bias), the threshold voltage becomes lower as compared with the state of no bias.
The semiconductor integrated circuit having the voltage regulators is provided, as a second internal circuit operating based on the first power voltage, with a substrate bias control circuit (71) which manipulates the substrate voltage of the switching elements, which form the first internal circuits, by utilization of the first power voltage and internal power voltage depending on the operation mode of the semiconductor integrated circuit. Specifically, for example, the switching elements are brought to the state of reverse substrate bias, so that the switching transistors have a higher threshold voltage and a smaller sub-threshold leak current, when the semiconductor integrated circuit is in the standby mode or sleep mode in which the internal circuits are not virtually operable. In the active mode, the substrate may be given no bias voltage application and left at the same voltage as the source of switching transistors.
As a specific control scheme, the substrate bias control circuit establishes the substrate voltages of the first internal circuits to be the internal power voltage and ground voltage during the first operation mode such as the active mode of the semiconductor integrated circuit, and establishes the substrate voltages to be the first power voltage and a negative voltage which results from step-down of the ground voltage during the second operation mode such as the standby mode or sleep mode.
(8) Design of Semiconductor Integrated Circuit
A semiconductor integrated circuit having the voltage regulators is designed by including step of layout of the regulators in the area having its width generally determined from the layout width of buffers and at positions near the external terminals of the first power voltage and ground voltage. The design of semiconductor integrated circuit will be facilitated by the provision of a cell library, from which voltage regulators that meet the power capacity demanded by the first internal circuits are selected.
(9) The semiconductor integrated circuit seen from another viewpoint of this invention has its voltage regulators made up of an amplifier section which is located in the area where the buffers and protection circuits in connection with the external terminals are formed and a transistor circuit section which is located in the area inner than the area of the buffers and protection circuits.
Specifically, for example, the semiconductor chip has a terminal area (1) where a number of external terminals are located, a first circuit area (outer side of area 2) where the buffers, protection circuits and a number of voltage regulators for stepping down a first power voltage supplied from the outside and received on a certain terminal to produce at least one kind of internal power voltage which is lower than the first power voltage are laid, a second circuit area (3) where first internal circuits which operate based on the internal power voltage are laid, and a third circuit area (4) where second internal circuits which operate based on the first power voltage are laid, with the amplifier section being included in the first circuit area. The transistor circuit section is included in the area between the first circuit area and the second circuit area, or in the area (inner side of area 2) between the first circuit area and the third circuit area.
In consequence, the latitude of layout of the voltage regulators increases.